The present invention relates to a semiconductor memory device provided with sense amplifiers.
FIG. 2 shows a core portion of a DRAM (dynamic random access memory) as an example of the semiconductor memory device provided with sense amplifiers. A pair of bit lines BLi and BLi are connected to one of the sense amplifiers SAi (i=0, 1, 2... ), respectively. Coupling capacitances between two of these two adjacent bit lines can be represented, for example, by Co between a pair of two bit lines BL1 and BL1, C.sub.1 between two adjacent bit lines BL1 and BL0, and C.sub.2 between two adjacent bit lines BL2 and BL1.
Further, FIG. 3 shows transistors which constitute sense amplifiers, respectively, in which each electrode 1, 2, 3 or 4 of each transistor is formed under and along each bit line BL0, BL1, BL1 or BL2 and connected to the bit line at each contact portion 5, 6, 7 or 8, thereof, respectively.
In the prior-art semiconductor memory device provided with sense amplifiers described above, however, since the distance between two adjacent bit lines (e.g. BL1 and BL0) is shorter than a distance between a pair of bit lines (e.g. BL1 and BL1) in general, there exists a problem in that interference noise is easily generated via each coupling capacitance. In addition, since the pitch distance between the two adjacent bit lines is increasingly shorten with the increasing integration rate of integrated circuits, the larger the coupling capacitances between the two adjacent bit lines, the more the interference noise.
However, when the potential between two adjacent bit lines fluctuates due to noise, since the potential between a pair of bit lines also fluctuates due to the interference noise via the coupling capacitances, the data-read potential generated when data are read out of each memory call via a pair of the bit lines also fluctuates, thus resulting in a problem in that erroneous data may be amplified when the data-read potential is amplified by the sense amplifier.
In practice, an assumption is made that high level data is read through the bit line BL1 and the potential of the bit line BL1 is at 1/2 V.sub.cc and that of BL1 is at a level a little lower than 1/2 V.sub.cc, where V.sub.cc denotes the supply voltage. Under these conditions, if the potential of the adjacent bit line BL0 fluctuates downward to the ground potential (V.sub.ss) due to noise, since the potential of the bit line BL1 drops below the potential of the bit line BL1 according to the noise level, so that an erroneous data is read out of the memory in case the data is amplified by the sense amplifier under those abnormal conditions. In this case, if the same level noise is superposed upon another adjacent bit line BL2 simultaneously, since the difference in potential between a pair of the bit lines BL1 and BL1 does not change, the above-mentioned erroneous operation can be prevented. However, if noise is superposed upon only one of the two adjacent bit lines BL0 and BL2 into unbalanced conditions, erroneous operation is liable to occur.
To overcome the problem caused by the abovementioned interference noise between two bit lines, there has been proposed a method of canceling two in-phase noises superposed upon the two adjacent bit lines by crossing a pair of bit lines as shown in FIG. 4. In this prior-art method, however, since the two bit lines are crossed, there arises another problems in that the chip area increases and therefore the device's core forming process is complicated.